Delay Aware Topology Generation for Network on Chip


Автор: Asrani Lit,Fariza Mahyan and Termimi Hidayat Mahyan

Язык: Английский

Год: 2015

Дополнительные характеристики

72 стр.

Цена на OZON:

365200 руб.


Network-on-Chip (NoC) is a scalable bandwidth requirement that using on-chip packet-switched micro-network of interconnects. NoC are based on System-on-Chips(SoCs) that traditionally large-scale multi-processors and distributed computing networks. The NoC performances analysis were evaluated in terms of throughput, queue size, loss and wait time. Meanwhile, Video Object Plane Decoder (VOPD) with 16 cores were used to measured the delay aware topology of NoC. Analysis performances of VOPD is based on the value of hops involved, since VOPD is divided into bisection and quadsection form. Overall, the report proved that the decreased number of hops of VOPD will give a low rate of delay in NoC performances.


Возможность скачать PDF:

Чтобы Delay Aware Topology Generation for Network on Chip скачать в PDF формате, нажмите на одной из кнопок социльных сетей: