Fault Tolerant Synthesis of Reversible Circuits

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History justifies the successful observance of Moore’s law on growth of packaging density per unit area. But the growth momentum is not likely to continue in near future due to various intrinsic limitations of conventional computing such as heat dissipation, speed of light, stray capacitance etc. In consequences reversible computing is gaining interest of the researchers due to its low power consumption, high speed and more packaging density. With high packaging density, the circuits may not remain free from faults. Fault Tolerant Synthesis of Reversible Circuits, introduces essentials of fault tolerance in reversible computing. This book first exploits parity-preserving characteristics of two newly proposed reversible gates which provide low cost parity-preserving based fault tolerance. To extend online testability of reversible circuits, the substitution of reversible gates has been presented. The online testing capabilities of some reversible gates have been identified and all available libraries for synthesis have been made online testable. Finally a tool is presented to implement all above substitutions and convert any reversible circuit to fault tolerant reversible circuit.

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